[From the February 1973 issue of Radio-Electronics magazine.]
See How it Works
Digital Clock on a Chip
Twelve- or 24 -hour displays, alarm, snooze-alarm and clock-radio
formats are offered in three MOS LSI circuits.
by Larry Sullivan
Mostek Corp., 1215 West Crosby Road, Carrollton, Tex.
A new family of three MOS IC's for use in electronic digital clocks makes
possible several different types of "single chip" clocks. These devices
have been introduced by Mostek Corporation of Carrollton, Texas.
All
members of this "clock family" are six-digit clocks that display time
in hours, minutes, and seconds. If only an hours and minutes clock is
desired the same IC may be used with only the two hours and two minutes
digits connected to the display. Outputs from these clocks may be connected
directly to fluorescent-anode display tubes. The high-voltage
output transistors allow fluorescent-anode display tubes to be driven
directly.
The MK 5017 P clock circuits are available now in an alarm clock
version, the MK 5017 P AA; a clock radio clock, the MK 5017 P AN; and
a unique combination clock /calendar the MK 5017 P BB. Time may be
displayed in either 12 -hour or 24 -hour formats.
The standard United States
60-Hz power line frequency may be used as a reference. If the clock is
intended for overseas operation where 50 Hz is the standard power line
frequency, the 50-Hz input frequency reference may be selected. The
MK 5017 P clock senses the power supply voltage and, if loss of power
is detected, displays all "eights". A backup battery may be used as
a power supply during temporary power loss. An adjustable 50-Hz or
60-Hz oscillator is included on the chip to furnish the frequency reference
during temporary loss of power.
The clock circuits require only a
single power-supply voltage, simplifying power supply design.
Time setting is easy, a matter of depressing and holding push-buttons which
allow the internal counters to increment at a 2-Hz rate. Each of the
minutes digits and the hours digits
may be set individually with no "carrys" generated to the more significant
digits. Thus, there is no "overrun" when setting the counter to a
time such as 2:59. In a counter in which "carrys" are allowed between
digits it is very easy to increment the minutes "9" by one extra count
and change all three digits so that the time reads 3:00. This makes it
necessary to reset the hours, tens of minutes, and minutes all over
again.
How it works
Figure 1 is a functional block diagram of the MK
5017 P digital clock circuit. A 1-Hz reference frequency is generated
for the time counter by the shaper-divider network from either a 50-Hz
or a 60-Hz input. The 50 /60-Hz input frequency may be derived from the
ac line or can be provided by an external crystal-controlled oscillator
and frequency divider for portable or automobile applications. When the ac
power line is used as a frequency reference, the user is faced with the
problem of temporary power loss. An on-chip temporary R-C oscillator
may be used to provide the frequency reference through temporary power
loss periods if a battery is used to provide chip power through the
power transient.
Time is measured by incrementing the time counter
at a l-Hz rate. The contents of the time counter are decoded from
BCD to seven-segment form and multiplexed out as serial digits. An
external resistor and capacitor may be used to control the
frequency of the scan-rate oscillator and thus control the rate at which
the display digits are scanned. This allows various display types with
different scanning characteristics to be used. Six-digit output strobes
identify the digit being multiplexed out of the circuit at a particular
time. The digits are scanned sequentially from least significant to
most significant. That is, the seconds digit is followed by the tens of
seconds digits which is followed by the minutes digit.
An alarm counter
may he set externally in the same manner as the time counter. While in
the alarm set mode, the contents of the alarm counter are displayed. In
the run mode when the alarm comparator detects coincidence between the
time counter and the alarm counter the alarm control circuit generates an
alarm tone. (The new Heathkit GC-1005 digital clock kit is built around a
version of the Mostek IC. The description of the alarm clock that
follows is the Heath clock. - Editor)
[Click for a larger image.]
MK 5017 P AA
The alarm clock version
of this chip, the MK 5017 P AA, features a 24-hour alarm. An alarm tone
at a frequency of approximately 700 Hz is generated on the chip by an
internal oscillator. This alarm tone, suitably buffered, may be coupled
into an inexpensive miniature speaker.
An AM /PM indicator is also
provided to allow setting the alarm on a 24-hour basis. The AM /PM
output, designated AM in Fig. 2. is pulled high to Vss by the transistor
to indicate AM. The AM output appears as an open circuit for PM.
If seconds are not being displayed the user may wish to use the optional
1-Hz output, available upon request, to blink the AM /PM indicator. This
provides a visual indication that the clock is running. Figure 2 shows
a typical circuit for a digital alarm clock using the MK 5017 P AA or
MK 5017 P AN and seven-segment fluorescent-anode display tubes. The
power supply consisting of transformer T1, rectifier diode D4,
and filter capacitor C3
generates approximately (-35V dc). Reference diode D3 reduces the power
supply output voltage to (-15V) for the IC's Vpp supply voltage. The
optional backup batteries shown may be used to prevent loss of time
during temporary power transients. Diode D2 remains OFF isolating the
batteries from the power supply in normal operation. If ac power is
removed, D2 is biased on by the batteries and provides the integrated
circuit with VDD supply voltage to prevent loss of time. While the ac
power is OFF the voltage on the 50/60 IN pin remains at a steady logical
one. The chip detects this condition and continues to measure time using
its own 50/60 Hz internal oscillators as a time base.
The frequency of
this oscillator may be set at either 50 Hz or 60 Hz by adjusting R1. When
ac power is present, the 60-Hz sinusoidal waveform from transformer
T1 is half-wave rectified by diode D1 and reduced from a (-35) volt
peak to a voltage one or two volts more negative than VDD by the
resistive divider composed of R2 and R3. Capacitor C2 serves as a noise-spike
suppressor and prevents false counts from noise spikes induced on the ac
line by equipment using SCR switching or universal motors.
Fluorescent-anode display tubes are shown in this example. As shown,
fluorescent-anode tubes may be driven directly by the clock circuit. The display
tube anodes are connected directly to the clock segment outputs. The
cathodes are driven by the individual digit outputs.
These display tubes have a common cathode and heaters. The 6.3
Vac winding of transformer T1 is reduced to approximately 4.2 Vac
by resistor R4 since the individual filament voltage is about 0.7
volt. This series filament "string" is biased at about (-25 Vac) by
transistor Q1.
Display brightness can be varied by adjusting variable
resistor R5 which sets the base voltage of transistor Q1. Q1 acts
as an emitter follower keeping a constant cathode bias on the display
tubes.
There are two function input pins, KA and KB. Both KA and KB pins
are sampled during each digit strobe. The intersection of the six-digit
output strobe lines and the KA and KB lines forms a matrix that is 6 X
2. That is, there are 12 potential locations where a spst switch may be
located. These switches may be used to define 12 separate functions
or modes of operation for the circuit. For example, at D6 time the KA
line is sampled to determine if the time set switch is closed. If the
time set switch is closed, the KA line will he pulled high to Vss by the
D6 output driver transistor. Isolation diodes D5 through D16 prevent
the digit outputs from being tied together in case of multiple switch
closures. For example, if the time set switch at the intersection of
D6 and KA and the hours switch at the intersection of D5 and KA were
both closed, the D5 and D6 digit strobe outputs would be tied together
if diodes D6 and D7 were omitted. At D5 time D6 is reverse-biased so
the D6 line is not pulled high by the D5 output. Similarly, at
D6 time D7 is reverse-biased so the D5 line is not pulled high by the
D6 output transistor. Since the KA and KB inputs are time multiplexed,
it is possible to connect 12 switches to only two input pins keeping
the circuit in a 24-pin package.
As shown in the INPUTS table on Fig. 2,
the switch located at the intersection of the D6 and KA line defines the
TIME SET mode. The switch is closed in the TIME SET mode. In this mode
of operation the contents of the time counter are displayed. Counting
is stopped in the TIME SET mode and the seconds and "tens-of-seconds"
digits are both held at zero. When the time set switch is released,
the clock begins running.
The switch located at the intersection of
D6 and KB is used to define the ALARM SET mode. In the ALARM SET mode
of operation the contents of the alarm counter are displayed. The time
counter continues running while the alarm is being set.
Closing the
switch located at the intersection of the D5 and KA lines causes the
hours digit to advance at the rate of two digits per second, (a 2-Hz
rate). Closing the switch located at the D5 and KB intersection causes
the minutes digit to advance at a 2-Hz
rate. If both the hours and the minutes switches are closed
simultaneously the "tens-of-minutes" digit advances twice each
second.
Enabling the alarm is accomplished by closing the switch located
at the intersection of the D4 and KB lines. When coincidence is detected
between the time counter and the alarm counter, the alarm tone is
generated for one hour if the enable alarm switch is closed.
When the alarm
"goes off" the snooze switch located at the intersection of the D4
and KA lines may be momentarily depressed to inhibit the alarm. After
seven minutes the alarm will go off again. This cycle may he repeated
indefinitely.
Twelve or twenty-four hour time displays may be selected
at any time without disturbing the time counter. Closing the switch
located at the intersection of the D3 and KA line results in a
twenty-four hour display.
For operation from a 50-Hz reference frequency,
the switch located at the intersection of the D3 and KB lines may be
closed. When this switch is open, the clock assumes a 60-Hz reference
frequency.
MK 5017 P AN
Clock radio clocks may be built using the MK
5017 P AN. This circuit includes all of the features normally found on
a clock radio clock. Both the alarm clock - MK 5017 P AA, and the clock
-radio clock - MK 5017 P AN are shown in Fig. 2. The circuitry shown by
dashed lines applies to the clock-radio clock. The remaining circuitry
is common to both.
In addition to all of the features found on the alarm
clock circuit the clock-radio circuit also has a radio sleep output
that may be used to keep a radio or other appliance on for selected
periods of time up to a maximum of two hours.
Radio sleep operation
is selected by closing switch SL at the intersection of the D1 and KA
lines in the input matrix. The switches located at the intersection of
the Dl and KB lines (SL1) at the intersection of the
D2 and KB lines (SL2), and at the intersection of the D2 and KA
lines (SL2), are used to select the desired sleep time. There are eight
possible combinations that may be achieved with these three switches, so
a total of eight different sleep times may be selected. The switches
are arranged in a binary code with the switch designated as SL1 being
the least significant bit.
The switch designated as SL4 is the most significant bit. The times that
may be selected, along with the switch closures required to program these
times, are presented in table.
After selecting the desired radio sleep
time from the table, close the sleep switch to start the timing interval.
It is not necessary to install three switches and remember the
binary code for sleep times. Instead, an eight-position three-pole
rotary switch may be used to easily and rapidly select sleep times.
In addition to the radio sleep feature the MK 5017 AA also has a radio
WAKE/SLEEP output. The radio WAKE/SLEEP output is operative during RADIO
WAKE and RADIO SLEEP operation. For RADIO WAKE operation the radio WAKE
/SLEEP output is on when the alarm counter and the time counter become
equal. The radio WAKE/SLEEP output remains active for one hour during
radio wake operation.
A display inhibit pin is included on the clock
-radio clock circuit. All of the segment- and digit-output transistors
are disabled (turned off) when the inhibit pin is connected to
Vss. This feature makes it possible to build a multifunction clock using
only one display, without any external multiplexing circuits.